Minutes, IBIS Quality Committee

07 December 2010

11:00-12:00 EST (08:00-09:00 PST)

ROLL CALL

Cisco Systems:                  Mike LaBonte*
Ericsson:                       Anders Ekholm*
Green Streak Programs:          Lynne Green
Huawei Technologies:            Guan Tao
IBM:                            Bruce Archambeault
IOMethodology:                  Lance Wang
Mentor Graphics:                John Angulo
Micron Technology:              Moshiul Haque, Randy Wolff
Nokia Siemens Networks:         Eckhard Lenski*
Signal Consulting Group:        Tim Coyle
Teraspeed Consulting Group:     Bob Ross*
Texas Instruments:              Pavani Jella

Everyone in attendance marked by *

NOTE: "AR" = Action Required.

-----------------------MINUTES ---------------------------
Mike LaBonte conducted the meeting.

Call for opens and IBIS related patent disclosures:

- No one declared a patent.

- Anders sent a presentation by email to Mike
  - We will discuss

AR Review:

- Mike post updated IQ checklist
  - Will do this today

- Mike post External Test Data and Test Load BIRD draft
  - Will do this today

- Mike test source voltage capture idea
  - Done

New items:

Presentation from Anders:
- We need to document what we are trying to achieve
- Drew 8 test fixtures
- Mike: Should these diagrams suggest probe points?
- Anders: slide 3 doesn't show the source
  - Maybe it could be defined by IBIS-ISS
- Mike: Walter would object
- Bob: It could be just SPICE
- Bob: The test case could be an I/V sweep, not just V/T
- Mike: Does [Test Data] allow any axis types?
- Anders: No, strictly time domain
- Bob: Both I and V can be measured using time domain
- Anders: The last case should be 8, not 4
- Anders: We need to decide how to handle probe ports
- Mike: It mostly needs a wrapper to say how the ports are used
  - A language to define internal probe nodes would not work well
- Bob: The number of ports does not need to be limited
- Mike: The [Test Data] can name the port it is measured from
- Bob: Will we measure only at the buffer?
- Anders: We need to settle that
- Bob: You might end up testing only pin parasitics
  - EDA tools might automatically look for just the bad cases
  - Test criteria would have to be known
- Mike: Maybe FSV criteria
- Bob: There may be a problem using the term "port" which has other meanings
- Mike: In SPICE it is often "terminals"
- Bob: We should not predefine the number of terminals
- Mike: Slide 6 stimuli need for both output and input
- Bob: Most tools use a voltage edge to trigger a buffer
  - Or a logical stimulus could be used
  - We could write a language for that
  - It could be just time-state pairs
- Mike: We might want to consider future simulations with more than 2 states
  - A table of state definitions could be used
  - Some states could be high, low, disabled, half-drive, full-drive
  - Then even strength changes can be captured
- Bob: That could end up being tool specific
  - We should not specify tests that the tool can't automate
- Anders: There is a question if the stimuli are external to the IBIS file
- Bob: For an output buffer the stimuli could be small
  - For input it might be a large PWL
  - It could be an external SPICE file
- This presentation will not be uploaded yet

Next meetings:
- Next meetings Dec 14 and Dec 21

Dec 14 agenda:
- Anders' presentation
- Mike's PWL studies

Meeting ended at 12:09 Eastern Time.